In some approaches, a memory array utilizes logic circuits and edge cells to connect the separate memory banks to I/O circuits. Each of the memory banks is sandwiched between two edge cells. Each of the logic circuits is sandwiched between two adjacent memory banks. With such arrangement, a circuit area of such memory array is too large. Accordingly, the length of the bit lines in the memory array is increased, and the wire loading in the memory array is thus increased. As a result, the performance of the memory array is reduced.